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IEEE 62530:2011

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IEEE 62530:2011

SystemVerilog - Unified Hardware Design, Specification, and Verification Language

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- Active.This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.

Author IEEE
Editor IEEE
Document type Standard
Format File
ICS 35.060 : Languages used in information technology
Number of pages 1294
Replace IEEE 62530 (2007)
Cross references IEC 62530 (2011-05), IDT
Year 2011
Document history IEEE 62530 (2011)
Country USA
Keyword 62530;IEEE 62530-2011